AI Accelerator Supply Chain Strains as T-Glass Shortage Bites

The AI accelerator story usually gets told through Nvidia's GPU roadmap or TSMC's foundry capacity. Tom's Hardware points to a different chokepoint. A Japanese company called Nittobo controls roughly 90% of the global supply of a specialist glass-fibre cloth known as T-glass, and that material sits inside every advanced AI chip package. Demand is now outstripping supply.

T-glass is a low-CTE glass cloth used in the organic core of IC substrates, the interconnect layer between a chip and its printed circuit board. It keeps large, high-heat packages dimensionally stable. As AI processors grow bigger and run hotter, that job gets harder. Tom's Hardware notes that keeping AI processors flat and functional comes down to T-glass.

Why supply cannot simply be switched on

Nittobo is tripling capacity at its Fukushima plant in Japan. The new supply will not reach the market until mid-2027. That timeline matters, because T-glass is not a commodity that can be substituted or spun up quickly. Making it takes specialised electric melting furnaces running at 1,600 to 1,700 degrees Celsius. The process involves melting silica-rich glass, spinning it into yarn and weaving it into an ultrathin cloth. Tom's Hardware reports that scaling this takes years of investment and expertise.

Another glass fibre, E-glass, is used the same way but is cheaper and mainly serves lower-end chips such as microcontrollers and older mobile processors. T-glass wins on thermal strength. For higher-powered chips, specifically massive 2.5D and 3D packaging, T-glass is the preferred option.

Bilal Hachemi, an analyst at Yole Group who tracks the IC substrate supply chain, told Tom's Hardware Premium that replacing T-glass is not easy because it "has specific dielectric and CTE values that work better for the AI chips, especially for the organic core." Hachemi also noted that the IC substrate industry has historically operated on thin margins, so even modest demand surges can trigger shortages. "Any increase in demand for build-up materials, ABF material, or T-glass can cause potential shortage, because it's against the basics of this industry," he said.

The numbers behind the squeeze

The current crunch comes from hyperscalers building ever-larger chip packages that consume more T-glass per unit. According to data from Nvidia cited by Tom's Hardware, interposer sizes have grown from 814mm2 for the Hopper architecture to 1,700mm2 for Blackwell, a 109% increase. The forthcoming Rubin and Feynman generations will scale further.

Bank of America estimates that Nittobo's electronic materials segment will see sales nearly double from 40.9 billion yen (266 million dollars) in 2025 to 87.7 billion yen by March 2028, with operating margins approaching 48%. Takashi Enomoto, research analyst at Bank of America, said demand for T-glass cloth "seems likely to grow more than originally expected." He added that the focus had been on thick T-glass for GPU and CPU semi packages, but that ultra-thin T-glass demand is now likely to rise as leading-edge devices shift away from E-glass.

The scramble for allocation has already produced an unusual sight. Hachemi said Nvidia reaching out directly to an upstream material supplier like Nittobo is unprecedented. "For the first time, we are seeing Nvidia, the end customer, reaching out to the upstream material suppliers to secure the capacity and make sure they will get it," he told Tom's Hardware. The worry is that once Nvidia locks down its share, rival chip buyers will be left fighting over the remainder.

Nittobo is not relying on Fukushima alone. It is doubling capacity of the raw yarn at its Taiwan plant and importing yarn back to Japan for cloth manufacturing. It has also struck a collaboration deal with Nanya Plastics to outsource some weaving. By 2027, roughly 20% of Nittobo's glass cloth is expected to be woven by Nanya, according to Tom's Hardware.

Bill Ho, an analyst at Yuanta, put the downstream picture bluntly: "With T-glass supply even more constrained now, suppliers are no longer providing lead times." Lead times for copper-clad laminates, a downstream material, have stretched from a normal 8 to 10 weeks to beyond 20, and prices have risen between 20 and 30%.

A parallel problem: how much memory inference actually needs

If materials constrain the supply side, memory bandwidth constrains the design side. At Hot Chips 2026, d-Matrix presented its Raptor 3D-DRAM accelerator for generative inference. ServeTheHome's write-up of the problem is worth reading as a statement of where AI hardware is stuck. Model weights keep growing, and the KV cache scales with context length multiplied by batch size. ServeTheHome gives the example of 64 users at 1M context producing roughly 935 GB of KV cache.

SRAM meets the bandwidth target but only at tiny scale. A pair of Corsair SRAM accelerator cards reaches roughly 300 TB/s at about 1 ns latency yet holds only about 4 GB, because a 6T SRAM cell is around 10 times larger than a DRAM cell and leakage runs to tens of watts at GB scale. HBM solves capacity but struggles on bandwidth: ServeTheHome reports d-Matrix citing a practical ceiling around 20 TB/s for HBM4 packages such as Nvidia's Vera Rubin and AMD's Instinct MI455. At 2.4 pJ/bit, pushing 100 TB/s through HBM would consume about 1.92 kW before any fabric traffic is counted.

d-Matrix's answer is to stack compute directly on top of DRAM dies, using a TSMC N4 logic die on a 3D DRAM die with 36 um face-to-face stacking. Vertical 3D IO comes in at around 0.3 to 0.4 pJ, roughly 10 times lower than HBM, according to ServeTheHome. At 32GB per card with 4-bit weights and an 8-bit KV cache, d-Matrix says it can fit a frontier model such as Kimi K3 at 1M context in a 72-card scale-up.

The engineering detail is where the difficulty lives. Each tensor engine needs a 128B flit per access, but with 3 banks per channel a single access returns 96B. Delivering one flit therefore takes two accesses and fetches 192B, wasting about 33% of bandwidth near 33 TB/s. d-Matrix's answer, stream blocking, shares one partial 32B access across three flits. Moving 100 TB/s at 0.37 pJ/bit works out to 296 W just for I/O.

Hyperscalers build their own, cautiously

Microsoft's Maia 200, presented at the same conference and covered by ServeTheHome, shows the other end of the trade-off. The 3nm chip has 140 billion transistors, six stacks of HBM3e, 7TB/second of HBM bandwidth, 10,000 TFLOPS of FP4 performance and a 750 Watt TDP, with an 820mm2 SoC die. Microsoft paired it with a fully connected quad topology and no scale-out networking at all. Everything is scale-up, across 128 racks and 6,000 chips in the slide shown. The company's Software Defined Local Access dataflow architecture keeps data access local and sets the dataflow at compile time, which buys determinism and cuts fabric traffic.

None of this loosens the materials constraint. Alibaba's Zhenwu V900, announced with 216GB of memory and 1,200GB/s of inter-chip bandwidth and mass production planned for Q1 2027, adds another buyer to the queue, as SemiEngineering's 25 September week-in-review notes. Samsung reportedly plans to at least double HBM4-family output in 2027, according to Seoul Economic Daily, and CXMT said its fifth-gen G5 DRAM entered mass production with an 11.95nm active-area half-pitch, though it did not disclose manufacturing yields. More memory and more accelerators mean more substrate, and more substrate means more T-glass.

The uncomfortable conclusion is that the binding constraint on AI compute in 2027 may not be lithography or HBM supply. It may be a woven glass cloth made by one company in Fukushima, with a competitor helping to weave it and a lead time nobody will quote.