Legacy chip supply chain: packaging, memory and materials now bite harder than fabs

On 1 October, Kate Underhill, future space transportation propulsion architect at the European Space Agency, told EE Times at the Pretzl Connect 2026 event in Budapest that space systems typically run "at least 10 years behind consumer electronics." Her example was blunt: ESA tried to order 20 laser diodes from a German supplier and was told the minimum order was 10,000 units.

That single anecdote carries the whole story of the legacy chip supply chain in late 2026. The constraint is no longer just who can etch the smallest transistor. It is who can get enough older parts, in small enough volumes, packaged and shipped reliably, while the newest AI silicon hoovers up capacity.

Packaging is the new choke point

The Register reported on 30 September that investment bank Jefferies, working with satellite imagery analytics firm SynMax, now sees advanced packaging as a hard ceiling on US datacenter buildout. SynMax estimates US deployments will rise from roughly 11 GW of gross capacity in 2025 to 16 to 18 GW in 2026, and puts the practical upper limit for 2027 in the low 20s of gigawatts. Announced pipelines imply more than 80 GW for 2028.

The arithmetic is simple. Existing advanced packaging capacity can support accelerators drawing the equivalent of about 13 GW of gross power, which converts to roughly 17.5 GW of total datacenter power once CPUs, memory and cooling are counted. Two additional packaging projects due in 2027 could add 6 GW. Jefferies also found that only half the US capacity scheduled for 2026 was under construction, and that work had yet to begin on as much as 80 percent of the 2028 pipeline.

Even chips fabbed on American soil may need to fly to Taiwan for packaging. That is a legacy problem wearing new clothes: the industry built its most advanced assembly in one place, and the older, cheaper packaging lines that serve automotive, industrial and space customers compete for the same staff and substrates.

Small orders, long cycles

Underhill's keynote, covered by EE Times, also flagged the buying conditions that keep legacy demand lumpy. Low satellite launch volumes stop space component buyers from securing favourable pricing, which is why ESA is pursuing "spin-in" strategies that adapt high-volume commercial off-the-shelf electronics for spaceflight.

Export controls add a second layer. "If there is any U.S. component on your satellite, then you have to comply with U.S. regulations," Underhill said, referring to the International Traffic in Arms Regulations. European manufacturers have tried to build ITAR-free satellites, but some specialised parts remain available only from foreign suppliers.

Space programs have traditionally relied on radiation-tolerant processors such as the SPARC-based LEON family, which ESA began developing in 1997. That is a two-decade-old architecture still flying, and still being ordered in batches of dozens rather than millions.

Memory tightens, and the old nodes feel it

MaxLinear's Puma 9 DOCSIS chip, announced on 28 September, is a case study in how memory economics now shape legacy product design. The company says the chip supports DDR5 as well as DDR4, explicitly to dodge "supply chain risk associated with legacy memory types." Puneet Sethi, SVP and GM of MaxLinear's network infrastructure and carrier business unit, told LightReading on 29 September that "as manufacturers are incentivized to move their capacity to DDR5, we think the DDR5 ecosystem and pricing and supply will become more relaxed than the stress that we see with DDR4."

MaxLinear claims the Puma 9 cuts customer premises equipment costs by 30 to 50 percent versus its predecessor, supports DOCSIS 3.1, 3.1+ and 4.0 on one SoC built on 8nm, and starts shipping in modems and gateways in 2027. It is also the first Puma generation on ARM rather than Intel x86, though the company says it will keep supporting both.

The Register noted on 30 September, in separate coverage, that Micron has warned RAM supply is set to worsen as its CEO celebrates "much higher" prices. Legacy nodes and legacy memory types are where the squeeze lands first.

China builds a parallel stack

On 30 September, Huawei's rotating chairman Eric Xu claimed in a Q&A-style release that the company's Ascend neural processing units had surpassed Nvidia in Chinese market share. "It's pretty hard to collect data about the market share of Nvidia in China, but based on the data we have collected, Ascend has surpassed Nvidia," Xu said, according to The Register. He added that Huawei lacks capacity to satisfy Chinese demand and has no plans to expand internationally in a fully fledged way.

The same day, DeepSeek open-sourced six software modules tailored to Huawei's Ascend chips, including an Ascend-compatible version of the TileLang programming language, according to the South China Morning Post. The stated aim is an "independent and controllable" software ecosystem for GPUs. TileLang's GitHub update says it now supports Huawei's Ascend 950 accelerators with native code generation, automatic scheduling and synchronisation.

Hardware is moving too. The SCMP reported on 1 October that Huawei's Richard Yu said the company had shipped about 100,000 Mate XT 2 trifold phones since the model's 12 September release, and that the Mate 90 series will adopt processors based on Huawei's Tau Scaling Law. A Bernstein report cited by the SCMP on 22 September estimated the Kirin 9050 Pro, the first Tau-based chip, uses technology equivalent to a 7nm node and outperformed Apple's 3nm A17 Pro in Geekbench 6 multicore tests, while remaining about 30 percent behind Apple's newest 2nm A20 Pro.

What the fab buildout still does not fix

New capacity keeps being announced. Gotion High-tech and Volkswagen's PowerCo plan about €3.22 billion ($3.67 billion) in battery and materials projects in Spain, Slovakia and Morocco, according to a Gotion stock exchange filing covered by CnEVPost on 28 September. The Spanish plant alone is sized at 29.1 GWh, with 8.4 GWh in Slovakia and 100,000 metric tons of LFP cathode material in Morocco. None of that is a semiconductor, but it is the same industrial logic: localise the inputs, accept a five-year build, and hope demand holds.

China is also pushing its own standards into the supply chain. The SCMP reported on 22 September that the State Administration for Market Regulation said a scaled-down "Micro Han Xin" code, a 2007-era symbology, had entered formal international standardisation, aimed at marking components too small for conventional labels. Data Matrix, created in the US nearly 40 years ago, is the incumbent.

For buyers of legacy silicon, the practical picture is this. Advanced packaging is booked out, memory is being reallocated to AI, minimum order quantities punish low-volume industries, and export controls can cut a component line overnight. The fabs are not the only gate anymore, and in some segments they are not the tightest one.