AI accelerator datacenter: OpenAI and Synopsys build chip design model as Senate blocks energy bill

Two stories about AI datacenters broke within 24 hours of each other this week, and they point in opposite directions. On one side, the tools used to design the accelerators are being rebuilt around AI models. On the other, the political system that is supposed to manage the electricity those accelerators consume just failed to pass a bill.

Start with the design side. According to The Decoder, OpenAI and Synopsys have signed a multi-year strategic partnership to build a specialized AI model for chip design called GPT-Synopsys. Synopsys makes electronic design automation tools, the software engineers use to design chips and semiconductors. The model combines OpenAI's AI technology with Synopsys' EDA tools, and OpenAI is licensing those tools for the project. The stated goal is a model that can reason about chip design and verification and directly operate Synopsys' tools. Engineers will delegate design objectives and review and approve the output. The model will run on OpenAI's infrastructure. Customer data will not be used for training and will be stored encrypted, according to both companies. Early tests with semiconductor customers are already underway, and the two companies will market the product together and share revenue.

Synopsys CEO Sassine Ghazi says AI could significantly speed up the design process. OpenAI co-founder Greg Brockman sees the partnership as a path to better chips and better AI. The Decoder also notes OpenAI is already working with Broadcom on chips built specifically for running AI models, and that the recently unveiled Jalapeno chip is very competitive against similar specialized chips.

Why design automation is suddenly the bottleneck

The timing is not accidental. A sponsor blog published by Semiconductor Engineering on 1 October argues that chip design has become the limiting factor in the race to build larger AI systems. The piece estimates an ASIC of typical complexity demands over 1,000 engineering months. It traces how EDA and hardware description languages such as Verilog, introduced in 1986, moved the bottleneck away from place and route and toward verification. The same outlet published a second sponsor blog the same day on PCIe over UCIe, describing how PCIe 8.0 traffic can cross chiplet boundaries using UCIe 3.0. The author warns that power management and reset flows are among the most common sources of complex integration bugs, because a timeout at the PCIe layer may originate from a delayed UCIe power-state exit. Both pieces are vendor-sponsored content from Siemens and Imagination respectively, so treat the claims as marketing-adjacent. The underlying engineering problem they describe is real.

On the same morning, Semiconductor Engineering published a third sponsor blog from Imagination on LLM performance metrics. It separates Time to First Token, which measures the prefill stage, from Inter-Token Latency, which measures decode. The distinction matters for anyone sizing accelerator fleets: prefill is compute-bound, decode is often memory-bandwidth-bound.

The political side stalled

Now the energy side. On Wednesday, Senate Democrats blocked the Ratepayer Protection Act by a 57-to-43 vote, falling just shy of the 60 votes needed to advance, according to The Guardian. Four Democrats joined Republicans in support: Maggie Hassan of New Hampshire, Amy Klobuchar of Minnesota, and both Georgia senators, Jon Ossoff and Raphael Warnock.

"Americans are calling for real solutions, real guardrails, real solutions on AI. Republicans' toothless datacenter bill completely misses the mark," Senate Democratic leader Chuck Schumer said in a floor speech before the vote.

The bill would have required electric utilities to consider adopting new standards so that datacenters pick up the costs of necessary upgrades to transmission, generation and distribution, which can otherwise be transferred to households and businesses. The House had approved it earlier this month by an almost unanimous vote. Ohio Republican Jon Husted, who championed the bill in the Senate, said big tech should be paying its own way rather than passing costs to local communities. The Guardian reports the vote was one of the last the Senate is expected to take before the 3 November midterms. The chamber is scheduled to conclude its work on Friday.

China closes ranks

The third thread this week is supply. On 30 September, The Decoder reported that Deepseek is releasing open-source programming tools for Huawei's Ascend chips, according to a post on Deepseek's official WeChat channel and Reuters. The centerpiece is TileLang, a language developed by researchers at Peking University that Deepseek argues offers a simpler programming model than Nvidia's CUDA. The two companies also optimized a supernode, a cluster of 128 Ascend 950 chips. The context is Nvidia's software moat. The Decoder cites an estimated four million developers worldwide who build with CUDA. It also cites SemiAnalysis, which tested OpenAI's Jalapeno inference chip and called the CUDA moat potentially dead, while cautioning that it only tested relatively easy scenarios of about 8,000 input tokens and 1,000 output tokens, and has not yet run the AgentX benchmark for multistep agent tasks. SemiAnalysis added that with AMD's current software stack, Nvidia would still come out cheaper per token even if AMD gave its hardware away. Huawei's chips were not part of that comparison.

Put together: the design tools are being rebuilt, the chips are being rebuilt, and the electricity bill is still unresolved.