AI datacenter buildout outruns chip packaging and power supplies

Huawei's rotating chairman Eric Xu claimed this week that the company's Ascend line of neural processing units has overtaken Nvidia in Chinese market share. "It's pretty hard to collect data about the market share of Nvidia in China, but based on the data we have collected, Ascend has surpassed Nvidia," Xu said in a Q&A-style release covered by The Register on 30 September. He added that Chinese buyers value assured supply: "Even though our chips may be less advanced, at least their supply is assured."

That claim lands as the supply question moves in the other direction. On the same day, The Register reported on a Jefferies analysis that puts US datacenter deployment at 16 to 18 GW of gross capacity in 2026, up from roughly 11 GW in 2025, and warns that advanced packaging, not wafer fabrication, is the emerging bottleneck.

The Jefferies report cites analytics firm SynMax, which uses weekly satellite imagery to track land clearing, first structures and construction progress at datacenter sites. That method separates projects actually moving dirt from projects that exist only as announcements. SynMax raised its 2026 forecast from 14 to 16 GW, but the amount of land being cleared has plateaued, leaving visible activity well short of the more than 80 GW implied by some 2028 pipelines and chip demand models.

Packaging becomes the ceiling

Advanced packaging combines multiple dies and memory components using high-density connections, and it sits between semiconductor production and operational datacenter capacity. SynMax estimates that existing packaging capacity could support accelerators drawing the equivalent of roughly 13 GW of gross power. After accounting for CPUs, memory, cooling and other loads, that converts into approximately 17.5 GW of total datacenter power. Two additional packaging projects expected online in 2027 could add another 6 GW, taking the practical ceiling into the low 20s of gigawatts unless capacity expands faster than forecast.

The Register notes that even chips manufactured on US soil may need to be sent overseas, typically to Taiwan, for packaging. That is a choke point that no amount of domestic fab construction removes on its own.

A previous Jefferies report found that only half the US capacity scheduled for 2026 was under construction, and that work had yet to begin on as much as 80 percent of the 2028 pipeline. Last year, London Economics International concluded that if all US bit barn projects forecast between 2025 and 2030 went ahead, power demand would exceed what the grid can deliver, according to The Register's account of that earlier work.

The Trump administration's export control policies governing the sale of AI accelerators to China haven't stopped homegrown Huawei from filling the void.

Huawei's answer to the packaging question is scale rather than process leadership. According to The Register, the company is currently deploying a 256,000-card Atlas 950 SuperCluster, and its newer architecture is designed to support training and inference for multi-trillion-parameter models and scale to as many as one million NPUs. Xu said Huawei does not have enough capacity to satisfy demand inside China, let alone expand internationally.

Design tools get an AI layer

If packaging is the physical bottleneck, design is the software one. On 30 September, OpenAI and Synopsys announced a multi-year strategic partnership to build a specialized chip design model called GPT-Synopsys, as reported by The Decoder. The model combines OpenAI's AI technology with Synopsys' electronic design automation tools, which OpenAI will license. The stated goal is a system that can "reason about chip design and verification, and to directly operate Synopsys' tools."

Engineers will delegate design objectives and then review and approve the output, according to both companies. The model will run on OpenAI's infrastructure, customer data will not be used for training and will be stored encrypted, and early tests with semiconductor customers are already underway. Both companies will market the product together and share revenue. Synopsys CEO Sassine Ghazi said AI could significantly speed up the design process, while OpenAI co-founder Greg Brockman framed the partnership as a path to better chips and better AI.

Startups are attacking the same problem from the manufacturing data side. EE Times reported on 30 September that Emergence AI is moving its neuroformal AI technology into active deployments with fabless semiconductor companies, and that integrated device manufacturers among its customers want the work extended into the fab.

Satya Nitta, co-founder and executive chairman of Emergence AI, told EE Times that demand exceeds supply and every fab is running at capacity. "You cannot make chips any faster, but what you can do is definitely get more chips per wafer yielding with AI," he said. Nitta described a system that pairs large language models with symbolic AI: "Algorithms propose, and symbolic AI verifies." He gave an example of an agent finding the same failure pattern across 30 percent of 1,500 products and suggesting a block redesign. Nitta became executive chairman and chief scientist about a month ago, when the company appointed Ian Eslick as CEO.

New silicon at the edges

Elsewhere in the dossier, chip announcements kept coming. Qualcomm used its annual Snapdragon Summit to announce the Snapdragon 8 Elite Gen 6 and Snapdragon 8 Elite Extreme Gen 6, according to ServeTheHome. The Extreme variant moves to TSMC's N2P process, LPDDR6 memory at 127.2 GB/s, Wi-Fi 8 with 4x4 MIMO and Qualcomm's X105 modem rated at 14.8 Gbps downstream; the standard Gen 6 keeps the N2P process but drops to LPDDR5X at 84.8 GB/s. This is the first generation to push Qualcomm's custom Oryon Arm cores to 5GHz.

On the broadband side, MaxLinear announced the Puma 9 DOCSIS chip. According to Light Reading's report on 29 September, the company claims the silicon can cut customer premises equipment costs by 30 to 50 percent against its predecessor while supporting DOCSIS 3.1, 3.1+ and 4.0 on a single SoC. MaxLinear says the D3.1+ configuration can deliver up to 12 Gbit/s downstream, and that the platform adds Wi-Fi 8 support, DDR5 memory compatibility and post-quantum cryptography readiness. The company expects modems and gateways based on the chip to start appearing in 2027, and says it has secured "multiple commitments" with CPE partners including Askey, Fritz! GmbH and Gemtek, plus support from Australian operator NBN Co.

Two details stand out. The Puma 9 is based on ARM rather than the Intel x86 platform that ran prior Puma generations; an industry source told Light Reading the move helps reduce power draw and some licensing costs. And the DDR5 support is explicitly a hedge against the DDR4 shortage, with MaxLinear's Puneet Sethi saying the company expects the DDR5 ecosystem to become "more relaxed" than DDR4. Dell'Oro Group's Jeff Heynen told Light Reading that most vendors will move to DDR5 for advanced Wi-Fi 8 units.

Handhelds wait on a chip

On the consumer side, The Verge reported on 1 October that AMD driver leaks have revealed a semi-custom chip codenamed Gainsborough, built on TSMC's N3P process, with import and export records showing AMD already shipping test equipment for validation. The name follows AMD's Final Fantasy convention: Aerith was the original Steam Deck APU and Sephiroth the OLED revision.

The Verge is sceptical that Gainsborough is the Steam Deck 2 chip. The package measures 25mm by 25mm, which is larger than the original Aerith at 19mm by 19mm, and leaker Gotou_3rd has suggested AMD's next handheld chips, the Ryzen Z3 and Z3 Extreme, will use the same 25mm by 25mm package with a 15 W target. Valve has said it wants a generational leap in performance and efficiency before building a sequel. The Verge also notes that AMD, not Valve, chose the Final Fantasy codenames, and that semi-custom chips have historically been shopped around to other customers before landing in their eventual device.

For datacenter planners, none of this changes the arithmetic. The packaging ceiling, the power wall and the construction lag are the constraints that decide how much AI capacity actually comes online, and the satellite imagery suggests the answer is less than the announcements imply.