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AI accelerator supply is the bottleneck, but packaging and power may cap US datacenter growth

Huawei's rotating chairman Eric Xu claimed on 30 September that the company's Ascend AI chips have overtaken Nvidia in Chinese market share, while new analysis from Jefferies and SynMax suggests US datacenter growth could be capped by advanced packaging capacity.

TechnologyAnalysisRachel NwosuPublished: 30 September 20263 min readSources 8
AI accelerator supply is the bottleneck, but packaging and power may cap US datacenter growth

Huawei's rotating chairman Eric Xu said on 30 September that the company's Ascend line of neural processing units had exceeded Nvidia in Chinese market share. He was speaking in a Q&A-style release reported by The Register. "It's pretty hard to collect data about the market share of Nvidia in China, but based on the data we have collected, Ascend has surpassed Nvidia," Xu said.

The claim could not be independently verified. Nvidia has not commented.

On the same day, DeepSeek open-sourced six software modules for Huawei's Ascend chips. The suite includes an Ascend-compatible version of TileLang, a programming language originally developed at Peking University. The South China Morning Post reported that the release aims to build an "independent and controllable" software ecosystem for GPUs. DeepSeek said Huawei "fully supported" the work, and the two companies also optimized a supernode cluster of 128 Ascend 950 chips, The Decoder reported.

That pairing matters because Nvidia's dominance rests partly on CUDA and an estimated four million developers worldwide, according to The New York Times, as cited by The Decoder. Research firm SemiAnalysis tested OpenAI's Jalapeño inference chip and called the CUDA moat "potentially dead." It cautioned that its tests covered only relatively easy scenarios and that Nvidia still leads on agent workloads.

Chip supply meets packaging and power limits

On 30 September, The Register reported that a Jefferies report shared with it, citing analytics firm SynMax, estimates US datacenter deployments will rise from roughly 11 GW of gross capacity in 2025 to 16-18 GW in 2026, above a previous forecast of 14-16 GW. SynMax puts the practical upper limit for 2027 in the low 20s of gigawatts. Land clearing for new projects has plateaued, though, leaving visible activity well short of the more than 80 GW implied by some announced pipelines and chip demand models for 2028.

Jefferies identifies advanced packaging as an emerging constraint. Even chips manufactured on US soil may need to be sent overseas, typically to Taiwan, for packaging. That creates a choke point between semiconductor production and operational datacenter capacity. SynMax estimates existing advanced packaging capacity could support accelerators drawing roughly 13 GW of gross power, or about 17.5 GW of total datacenter power after accounting for CPUs, memory, cooling and other loads. Two additional packaging projects expected online in 2027 could add another 6 GW, taking the practical ceiling into the low 20s unless capacity expands faster than forecast.

The pressure is not only about chips. On 30 September, EE Times reported that Emergence AI is moving its neuroformal AI technology into active deployments with fabless semiconductor companies. Integrated device manufacturers among its customers are asking it to extend the work into the fab. Satya Nitta, co-founder and executive chairman, told EE Times: "You cannot make chips any faster, but what you can do is definitely get more chips per wafer yielding with AI." He said demand exceeds supply and every fab is running at capacity, so more wafers cannot be pushed through.

On the design side, Tom's Hardware reported on 30 September that Cadence, Synopsys and Siemens EDA all claim notable improvements in agentic AI for chip design in 2026, with varying claims of autonomy. Cadence said its agent reached what it calls Level 5 autonomy at Computex on 1 June. Synopsys said its spec-to-RTL workflow shown on 11 March reached "L4," and Siemens launched its agent on 16 March with "self-verifying" loops announced on 26 July. Tom's Hardware noted that all the speed improvements are vendors' or customers' own figures, often with "up to" or "early evaluation" caveats, and measure different things against different baselines.

OpenAI and Synopsys signed a multi-year strategic partnership to build GPT-Synopsys, a specialized AI model for chip design, The Decoder reported on 30 September. The model will run on OpenAI's infrastructure, and customer data won't be used for training, according to both companies. Early tests with semiconductor customers are already underway, and the two companies will market the product together and share revenue.

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Sources

8
  1. 01America is planning more AI datacenters than its chip supply can fillEN
  2. 02Huawei boss claims homegrown AI chip sales top Nvidia in ChinaEN
  3. 03OpenAI and Synopsys team up to build an AI model that designs chips like a seasoned engineerEN
  4. 04China's AI industry closes ranks as Deepseek ships open-source software for Huawei's Ascend chipsEN
  5. 05The state of agentic AI in chip design tools in 2026EN
  6. 06AI Chip Design WeekEN
  7. 07Emergence AI Targets Fabless Chipmakers With Neuroformal AIEN
  8. 08China's DeepSeek open-sources tools to help Huawei chips supplant Nvidia in AIEN

All figures and quotations in this text come from the sources listed below.

Content prepared by the editorial team with AI assistance.

Rachel Nwosu

Rachel Nwosu

AI, models and technology

Rachel Nwosu covers AI, models and technology for FLASH24, working from public model documentation, benchmark releases and repository histories rather than press summaries, and she skips announcements that arrive without reproducible numbers. She checks training-data claims against dataset cards and reruns reported metrics where code is available. She spends much of her week interviewing researchers and engineers, tracking model launch calendars, and comparing vendor benchmarks with independent evaluations. Outside the desk she runs 3D printers, restores old computers, and tests how models learn from internet junk. She does not publish benchmark figures she cannot trace to a source.

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