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AI Accelerators Meet the Datacenter Grid: Supply, Power and the 2027 Ceiling

On 30 September, Huawei's rotating chairman Eric Xu claimed the company's Ascend chips had overtaken Nvidia in Chinese market share. The same day, analysts and satellite data pointed to a very different constraint on the US side: not enough packaged accelerators to fill the datacenters already being built.

TechnologyExplainerRachel NwosuPublished: 30 September 20267 min readSources 8
AI Accelerators Meet the Datacenter Grid: Supply, Power and the 2027 Ceiling

On 30 September, Huawei's rotating chairman Eric Xu said its Ascend line of neural processing units has surpassed Nvidia in Chinese market share. "It's pretty hard to collect data about the market share of Nvidia in China, but based on the data we have collected, Ascend has surpassed Nvidia," he said in a Q&A-style release, as reported by The Register.

The same day, separate reporting from The Register laid out the opposite problem in the United States: not enough advanced packaging capacity to fill the datacenters on the drawing board.

The US pipeline versus the packaging bottleneck

According to a Jefferies report shared with The Register, server farm construction across America is proceeding, but permitting, power access and supplies of packaged AI accelerators are holding projects back. The investment bank cites analytics firm SynMax, which uses weekly satellite imagery to track land clearing, first structures and construction progress. That lets it separate projects actually advancing from those merely announced. SynMax now estimates US deployments rising from roughly 11 GW of gross capacity in 2025 to 16-18 GW in 2026, up from a previous forecast of 14-16 GW. For 2027, it puts the practical upper limit in the low 20s of gigawatts.

That ceiling is not about wafer starts.

Jefferies identifies advanced packaging as the emerging constraint. There, accelerator dies are combined with components such as high-bandwidth memory using high-density connections. Even chips fabricated on US soil may need to be sent overseas, typically to Taiwan, for packaging. SynMax estimates existing advanced packaging capacity supports accelerators drawing the equivalent of roughly 13 GW of gross power. After accounting for CPUs, memory and cooling, that converts to about 17.5 GW of total datacenter power. Two additional packaging projects expected in 2027 could add another 6 GW, taking the practical ceiling into the low 20s unless capacity expands faster than forecast.

Land clearing has plateaued, The Register notes, leaving visible activity well short of the more than 80 GW implied by some announced project pipelines and chip demand models for 2028. A previous Jefferies report found only half the US capacity scheduled for 2026 was under construction, with work yet to begin on as much as 80 percent of the 2028 pipeline. This is not the first warning: last year a report from London Economics International concluded that if all the bit barn projects forecast for the US between 2025 and 2030 went ahead, it would require 9 (the dossier cuts off there).

China's substitution push

Beijing's response to US export controls has been to push domestic alternatives. The Register notes that after Washington imposed licensing requirements on Nvidia's and AMD's China-spec accelerators in April 2025, the Commerce Department reversed course that summer and later reached an arrangement to cut the US government in on a percentage of certain China-bound chip sales. By late last year, Nvidia was allowed to sell H200-series parts to approved Chinese customers for the first time. But the earlier H20 blockade had already prompted Chinese officials to pressure datacenter operators to move away from foreign accelerators.

During Nvidia's Q2 earnings call, executives said shipments of a small volume of H200 accelerators to the region amounted to less than 1 percent of its datacenter revenues.

Xu's pitch leans on that uncertainty: "Even though our chips may be less advanced, at least their supply is assured, so that you don't have to worry about chip supply day in and day out." He added that for the Chinese government, the domestic industry and Huawei, "the path forward is undoubtedly to push for full self-sufficiency in terms of chips and the entire semiconductor value chain." Huawei is currently deploying a 256,000-card Atlas 950 SuperCluster, with a newer architecture designed to scale to as many as one million NPUs. Xu also downplayed international ambitions: "We don't have enough capacity to satisfy the demand in China. We don't have plans to expand the international market in a fully-fledged way."

Software is moving in the same direction. On Wednesday, Chinese AI startup DeepSeek open-sourced a suite of core tools tailored for Huawei's Ascend chips, according to the South China Morning Post. Hangzhou-based DeepSeek released six software modules mirroring its prior open-source tools for Nvidia's chips. The aim, per a post on its official WeChat account, is to build what it calls an "independent and controllable" software ecosystem for GPUs. Among them is an Ascend-compatible version of TileLang, a programming language for high-performance kernels; the project's GitHub page says it now officially supports Huawei's Ascend 950 accelerators with native code generation, automatic scheduling and synchronisation.

Design tools, yields and the demand side

The design layer is also being automated. On 30 September, OpenAI and Synopsys said they had signed a multi-year strategic partnership to build a specialised AI model for chip design called GPT-Synopsys, according to The Decoder. OpenAI is licensing Synopsys' EDA tools, with the goal of a model that can "reason about chip design and verification, and to directly operate Synopsys' tools." The model will run on OpenAI's infrastructure; customer data will not be used for training and will be stored encrypted, both companies said. Early tests with semiconductor customers are underway, and the two will market the product together and share revenue. Synopsys CEO Sassine Ghazi says AI could significantly speed up design; OpenAI co-founder Greg Brockman frames the partnership as a path to better chips and better AI.

Tom's Hardware, in its AI Chip Design Week coverage, reports that Cadence, Synopsys and Siemens EDA all pitch agentic AI with varying autonomy claims. Cadence said on 1 June that its ChipStack agent reached what it calls Level 5 autonomy; Rob Knoth, senior group director of strategy at Cadence, told Tom's Hardware Premium the demo was "what we call bounded Level 5 in one domain," with most of the super-agent tech at "advanced Level 4." Synopsys said its spec-to-RTL workflow shown on 11 March reached "L4" and now claims L5 for long-horizon agents; Siemens launched its agent on 16 March with self-verifying loops announced on 26 July. Tom's Hardware notes all speed improvements are vendors' or customers' own figures, with "up to" or "early evaluation" caveats, and that the only evaluator Synopsys named in July, AMD, has not provided analysis beyond an endorsement.

Outside the big three, Emergence AI told EE Times at SEMICON India 2026 that it is moving its neuroformal AI technology into active deployments with fabless semiconductor companies, while integrated device manufacturers among its customers want the work extended into the fab. Co-founder and executive chairman Satya Nitta said demand exceeds supply and every fab runs at capacity, so the way to ease the shortage is more chips per wafer yielding. "You cannot make chips any faster, but what you can do is definitely get more chips per wafer yielding with AI," he said. Nitta described agents finding the same failure pattern across 30 percent of 1,500 products, in a ring oscillator block, and suggesting a redesign. He became executive chairman and chief scientist about a month ago when Emergence appointed Ian Eslick as CEO.

On the hardware comparison side, rental marketplace Flopper.io lists live rates for the accelerators in question: an H100 SXM5 80GB at $1.79 per hour, an H200 SXM at $2.09, a B200 SXM 180GB at $4.09 and a B300 SXM 262GB at $4.99, alongside eight-GPU systems such as HGX B200 at $32.72 per hour and HGX H100 at $14.32. Those figures are marketplace quotes, not vendor list prices, and availability varies.

Put together, the picture is of an industry where the binding constraint keeps moving: from wafers to packaging, from packaging to power and land, and from US supply to Chinese substitution. The numbers from SynMax and Jefferies suggest the US builds what it can package, and that the gap between announced gigawatts and energised ones will not close on its own.

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Sources

8
  1. 01Huawei boss claims homegrown AI chip sales top Nvidia in ChinaEN
  2. 02America is planning more AI datacenters than its chip supply can fillEN
  3. 03China's DeepSeek open-sources tools to help Huawei chips supplant Nvidia in AIEN
  4. 04OpenAI and Synopsys team up to build an AI model that designs chips like a seasoned engineerEN
  5. 05The state of agentic AI in chip design tools in 2026EN
  6. 06AI Chip Design WeekEN
  7. 07Emergence AI Targets Fabless Chipmakers With Neuroformal AIEN
  8. 08Datacenter GPU Comparison: AI Accelerator Specs & Peak PerformanceEN

All figures and quotations in this text come from the sources listed below.

Content prepared by the editorial team with AI assistance.

Rachel Nwosu

Rachel Nwosu

AI, models and technology

Rachel Nwosu covers AI, models and technology for FLASH24, working from public model documentation, benchmark releases and repository histories rather than press summaries, and she skips announcements that arrive without reproducible numbers. She checks training-data claims against dataset cards and reruns reported metrics where code is available. She spends much of her week interviewing researchers and engineers, tracking model launch calendars, and comparing vendor benchmarks with independent evaluations. Outside the desk she runs 3D printers, restores old computers, and tests how models learn from internet junk. She does not publish benchmark figures she cannot trace to a source.

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