AI Accelerators Hit a Materials Wall: T-Glass, HBM Limits and the Design Squeeze

Nittobo's T-glass is a low-CTE glass cloth used in the organic core of IC substrates, the interconnect layer between a chip and its printed circuit board. Tom's Hardware reported on 9 March that the material keeps large, high-heat packages dimensionally stable, and that demand has outrun supply badly enough to hit AI accelerator supply chains.

Prices are up between 20 and 30%. Lead times for downstream materials such as copper-clad laminates have stretched from a normal 8 to 10 weeks to beyond 20. "With T-glass supply even more constrained now, suppliers are no longer providing lead times," Bill Ho, an analyst at Yuanta, told Tom's Hardware.

The constraint is not easy to engineer around. T-glass needs specialised electric melting furnaces running between 1,600 and 1,700 degrees Celsius. Melting silica-rich glass, spinning it into yarn and then weaving it into ultrathin cloth takes years of investment and expertise to scale. Nittobo is tripling capacity at its Fukushima plant, but the new supply will not reach the market until mid-2027.

Why Nvidia is calling upstream

What makes this crunch unusual is who is doing the scrambling. Hyperscalers are ordering ever-larger chip packages, and each generation consumes more T-glass per unit. According to Nvidia data cited by Tom's Hardware, interposer sizes grew from 814mm² on Hopper to 1,700mm² on Blackwell, a 109% increase, with the forthcoming Rubin and Feynman generations scaling further.

Bilal Hachemi, an analyst at Yole Group who tracks the IC substrate supply chain, said T-glass has specific dielectric and CTE values that work better for AI chips, especially the organic core. Substrate makers run thin margins, he added, so even modest demand surges trigger shortages. He also called Nvidia's direct approach to an upstream material supplier unprecedented: "For the first time, we are seeing Nvidia, the end customer, reaching out to the upstream material suppliers to secure the capacity and make sure they will get it."

Once Nvidia locks down its share, rival chip buyers compete for what remains. Nittobo is doubling raw yarn capacity at its Taiwan plant, importing yarn back to Japan for weaving, and has struck a collaboration with Nanya Plastics to outsource some weaving. By 2027, roughly 20% of Nittobo's glass cloth is expected to be woven by Nanya, a competitor. Bank of America estimates Nittobo's electronic materials segment will nearly double sales from ¥40.9 billion ($266 million) in 2025 to ¥87.7 billion by March 2028, with operating margins approaching 48%.

The memory wall moves in parallel

The packaging squeeze is not the only physical limit closing in on accelerator design. At Hot Chips 2026, d-Matrix presented Raptor, a 3D-DRAM accelerator for generative inference, and the argument was mostly about bandwidth economics. Model weights keep growing, and the KV cache scales with context length multiplied by batch size: 64 users at 1M context can mean roughly 935 GB of KV cache.

HBM solves capacity but struggles on bandwidth. ServeTheHome reported d-Matrix citing a practical ceiling around 20 TB/s for HBM4 packages such as Nvidia's Vera Rubin and AMD's Instinct MI455, limited by pin speed, I/O width per base die and package beachfront of roughly 8 to 16 stacks. At 2.4 pJ/bit, pushing 100 TB/s through HBM consumes about 1.92 kW before fabric traffic is counted. d-Matrix's alternative stacks a TSMC N4 logic die on top of a 3D DRAM die using 36 micrometre face-to-face stacking, which the company describes as proven, low-cost, high-volume and high-yield.

Microsoft's Maia 200, detailed at the same conference, takes a different route: a 3nm chip with 140 billion transistors, six HBM3e stacks, 7TB/second of HBM bandwidth, 10,000 TFLOPS of FP4 throughput and a 750 Watt TDP. ServeTheHome reported that Microsoft pairs it with a fully connected quad topology and scale-up-only networking, with no scale-out fabric, betting on unified Ethernet across 128 racks and 6,000 chips.

Design tools fill the gap

With physics tightening, the industry is leaning harder on AI-assisted design. Nvidia's Tim Costa said on a call with journalists, reported by The Next Platform on 27 July, that the industry is expected to produce 2 trillion chips and process about 41 million wafers a month by 2030, and that traditional design processes cannot keep pace. Cadence claims its AI Super Agents can run hundreds of simulations to deliver 40 times faster register-transfer level validation, while Synopsys says its autonomous verification workflow reaches validated RTL 50 times faster than other platforms.

Those claims need verification before sign-off, and SemiEngineering noted on 25 September that the shift toward specialised agents is creating new problems around orchestration, integration and guardrails. Cadence reported about 24% lower area and 18% lower power for its spec-to-RTL agent versus pure foundation model code generation.

None of this resolves the substrate bottleneck. Nittobo's new Fukushima output arrives mid-2027, and the demand curve from bigger interposers and longer contexts is not flattening.