TSMC 2nm capacity could reach 120,000 wafers a month by end-2026, EDN reports

EDN reported on Monday, in a report relayed by Investing.com, that customers including Apple, Nvidia, AMD, Qualcomm and MediaTek have recently raised orders for TSMC's 2nm family capacity by 10% to 20%. The 120,000-wafer figure is an industry-source estimate, not a TSMC disclosure. The report said TSMC is bringing five 2nm fabs online in 2026, two in Hsinchu and three in Kaohsiung, citing TSMC senior vice president Hou Yung-ching.

Hou said first-year 2nm wafer output would be 45% higher than the first-year output of 3nm in 2023. The report put 2nm capacity growth at a compound annual rate of 70% from 2026 to 2028. The 120,000 figure would put TSMC near the 110,000 to 140,000 wafers a month it had been expected to reach by the end of 2027, according to Wccftech.

High-performance computing accounted for 66% of TSMC's second-quarter 2026 revenue, up from 60% a year earlier, according to GuruFocus. Chips at 7nm and below made up 77% of wafer revenue, with 2nm at 3%.

Production started at Kaohsiung

Volume production began in the fourth quarter of 2025. TSMC disclosed it on its 2nm technology page rather than in a press release; the page states N2 "has started volume production in 4Q25." TechSpot reported that Fab 22 near Kaohsiung started first, while earlier expectations had pointed to Fab 20 near Hsinchu, adjacent to TSMC's global R&D center. Fab 20 is now expected to begin mass production later. eeNews Europe noted that TSMC lists Fab 20 and Fab 22 as its 2nm production facilities.

Starting at Kaohsiung marks a change in TSMC's usual ramp strategy. The company typically introduces new process nodes with smaller mobile chips before expanding to high-performance computing products. This rollout includes both categories, covering designs for smartphones and AI and HPC chips, TechSpot reported. Chief executive C.C. Wei said on an October 2025 earnings call that TSMC expected "a faster ramp in 2026, fueled by both smartphone and HPC AI applications."

What N2 changes

N2 is TSMC's first generation of gate-all-around nanosheet transistors, replacing the FinFET design used at earlier nodes, according to TechSpot. The gate wraps the channel, which tightens electrostatic control and reduces current leakage. Against N3E, TSMC targets 10% to 15% more performance at the same power, or 25% to 30% less power at the same performance. Density rises about 15% in mixed designs that include logic, analog and SRAM, and up to 20% in logic-only layouts.

N2 also adds super-high-performance metal-insulator-metal capacitors to the power delivery network. TSMC says they carry more than twice the capacitance density of its earlier capacitor design while halving sheet and via resistance, according to TechSpot. eeNews Europe noted that design rules, libraries, SRAM and the I/O mix decide the real outcome for any single product.

Cost and next nodes

TSMC has said the 2nm ramp would cost about 3 to 4 percentage points of gross margin in the second half of 2026, Barchart reported. Seeking Alpha lists overseas fab dilution as a separate drag, expected to widen to 3% to 4%. The company guided third-quarter 2026 gross margin to 65% to 67%, down from 67.7% in the second quarter. Second-quarter gross margin had risen 1.5 percentage points sequentially on revenue of NT$1.27 trillion, or $40.2bn, TechTimes reported.

TSMC lifted 2026 capex guidance to $60bn to $64bn from $52bn to $56bn, with 70% to 80% of the budget for advanced process technologies, TechTimes reported. TSMC expects fourth-quarter revenue of $52.3bn to $54.3bn, as much as 61% higher year on year, with accelerating 2nm production supporting the year-end, Digitimes reported.

N2P, which adds performance and power benefits on top of N2, is scheduled for volume production in the second half of 2026. A16, which uses TSMC's Super Power Rail backside power delivery, is on the same schedule and targets HPC products with dense power delivery networks, TechSpot reported.