America is planning more AI datacenters than its chip supply can fill

Satellite imagery shows American datacenter construction is speeding up. It still is not fast enough to meet some of the more exuberant forecasts for 2028, and chip packaging has emerged as a fresh bottleneck. That is the finding of a Jefferies report shared with The Register, which published details on 30 September.

Jefferies cites analytics firm SynMax, which uses weekly satellite imagery to track land clearing, the appearance of first structures, and construction progress at datacenter sites. The method separates projects that are actually advancing on the ground from those that have merely been announced.

SynMax now estimates US deployments will rise from roughly 11 GW of gross capacity in 2025 to 16-18 GW in 2026, up from its previous forecast of 14-16 GW. It puts the practical upper limit for 2027 in the low 20s of gigawatts.

Land clearing has plateaued

The amount of land being cleared for new projects has plateaued, according to the same data. Visible activity is well short of the pace required to deliver the more than 80 GW implied by some announced project pipelines and chip demand models for 2028. That chimes with a previous Jefferies report. It found that only half the US capacity scheduled for 2026 was under construction, and that work had yet to begin on as much as 80 percent of the 2028 pipeline. Permitting, access to power, and supplies of packaged AI accelerators continue to hold projects back, the bank says.

This is not the first warning that chip supplies could limit datacenter expansion. The Register notes that last year a report from London Economics International concluded that if all the bit barn projects forecast for the US between 2025 and 2030 went ahead, it would require far more power than the grid is currently set up to deliver.

Packaging is the choke point

Jefferies identifies advanced packaging as another emerging constraint. Fabricating enough accelerator dies is only part of the job: they must also be packaged with components such as high-bandwidth memory before OEMs can install them in servers. Advanced packaging combines multiple dies and memory using high-density connections, an approach used in many advanced CPUs and AI accelerators.

Even chips manufactured on US soil may need to be sent overseas, typically to Taiwan, for packaging, creating a choke point between semiconductor production and operational datacenter capacity. SynMax estimates existing advanced packaging capacity could support accelerators drawing the equivalent of roughly 13 GW of gross power.

After accounting for CPUs, memory, cooling and other loads, it converts that figure into approximately 17.5 GW of total datacenter power. Two additional packaging projects expected to come online in 2027 could support another 6 GW, taking the practical ceiling into the low 20s unless capacity expands faster than forecast.

The packaging crunch sits alongside a memory squeeze. Micron's CEO has said RAM supply is set to worsen, with "much higher" prices, according to a Register report published 30 September. That matters because accelerators and the servers around them both depend on the same constrained supply chain.

Huawei claims the China lead

On the other side of the export controls, Huawei's rotating chairman Eric Xu claimed in a Q&A-style release this week that its Ascend line of neural processing units had exceeded Nvidia in Chinese market share.

"It's pretty hard to collect data about the market share of Nvidia in China, but based on the data we have collected, Ascend has surpassed Nvidia," Xu said, according to The Register.

Xu added that Huawei's chips may be less advanced, but their supply is assured. "Chinese people have a keen sense of urgency, and will not accept a future in which others decide whether or not we can have access to certain products," he said. The Register reported the comments on 30 September.

Nvidia's own numbers offer a counterweight. During its Q2 earnings call, executives said shipments of H200 accelerators to China amounted to less than 1 percent of its datacenter revenues. Ars Technica reported on 28 September that China's Ministry of Industry and Information Technology has asked Alibaba and ByteDance to share plans to buy Nvidia's RTX Pro 5500 chips, with expectations those parts could be put into servers.

Ars Technica also reported that Jensen Huang has blamed US export controls for cutting Nvidia's share of China's advanced AI chip market from about 95 percent to zero. It cited reporting by The Information and an interview with Stephen Witt, author of a book on Huang, who told NPR that the Nvidia chief is now "the president's most influential adviser on technology issues".

DeepSeek builds a Huawei software stack

Software is moving in the same direction. DeepSeek on 30 September open-sourced six software modules tailored for Huawei's Ascend AI chips, according to the South China Morning Post. The Hangzhou-based AI developer said the release aims to build an "independent and controllable" software ecosystem for GPUs.

Among the modules is an Ascend-compatible version of TileLang, a programming language for high-performance kernels. Its GitHub page now lists official support for Huawei's Ascend 950 accelerators, offering native code generation, automatic scheduling and synchronisation, the SCMP reported.

Huawei is also pushing its chip designs into phones. At a press briefing on Tuesday, consumer business chief Richard Yu Chengdong said the company had shipped about 100,000 Mate XT 2 trifold handsets since the model's release on 12 September, the SCMP reported on 1 October. Yu said the phone, the first to integrate mobile processors using Huawei's LogicFolding architecture based on its Tau Scaling Law, is on track to surpass 1 million in total sales.

Separately, Bernstein estimated in a 22 September note that Huawei's Kirin 9050 Pro chip narrowed the gap with Apple to about three years, from roughly four years previously, while still sitting around 30 percent behind Apple's newest 2nm A20 Pro in performance.

Design tools become the new front

Meanwhile the tooling that produces accelerators is itself being rebuilt around AI. OpenAI and Synopsys signed a multi-year partnership to build a specialized chip design model called GPT-Synopsys, The Decoder reported on 30 September. The model is intended to reason about chip design and verification and operate Synopsys' EDA tools, with engineers delegating objectives and approving output.

Cadence, Synopsys and Siemens EDA are all shipping agentic design tools, Tom's Hardware reported on 30 September. Cadence said in June its agent reached what it calls Level 5 autonomy, with a senior director describing the demo as "bounded Level 5 in one domain". Synopsys said its spec-to-RTL workflow reached L4 in March, and now claims L5 for long-horizon agents. Siemens launched its agent on 16 March with self-verifying loops announced on 26 July.

Tom's Hardware is blunt about the evidence base: all the claimed speed improvements are the vendors' or their customers' own figures, many carrying "up to" or "early evaluation" caveats, and the only evaluator Synopsys named in July, AMD, has not provided analysis beyond an endorsement. In an earlier piece on 29 September, Tom's Hardware traced the progression from machine learning optimization tools to agents that operate EDA software directly.

None of this resolves the near-term arithmetic. If advanced packaging capacity is the ceiling, then announced pipelines and chip demand models for 2028 describe a datacenter buildout that the supply chain cannot currently fill, no matter how much land gets cleared.