TSMC packaging price rise looms as AI suppliers keep building capacity

Suppliers keep building while the warnings pile up

Firms across the AI supply chain announced fresh investment in manufacturing capacity in recent weeks, BriefAsia reported on 3 November. The investment spans fabrication, advanced packaging, optical components and data centres. Third-quarter results from key suppliers showed revenue and margin improvements tied to AI orders. Several cited order visibility extending into the first half of 2027. In Taiwan, multiple packaging houses are expanding interposer and chip-on-wafer-on-substrate capacity. They aim to meet demand for high-bandwidth memory integration and multi-die modules. South Korean memory manufacturers have moved next-generation HBM production timelines forward. Additional clean-room space is coming online ahead of earlier schedules.

Packaging capacity, not just wafer fabs, now sets what AI accelerators cost and when they ship. A reported 10% to 20% CoWoS price move would feed into server and GPU pricing. Equipment lead times of six to eight months stretch any new line. Neither report says when a TSMC increase would take effect.

Capacity reservations extend well into next year, BriefAsia reported. They cover advanced packaging and leading-edge logic nodes.

The price signal out of Taiwan

The Commercial Times reported that TSMC is poised to raise advanced chip packaging prices by as much as 20%. Investing.com carried the story. Foundries and outsourced assembly and test providers were preparing for increases of 10% to 20%. The increases cover chip-on-wafer-on-substrate packaging, which is widely used in advanced AI processors. remio reported on 29 October that a CoWoS price increase was under consideration as Nvidia packaging demand strains supply.

Equipment lead times have lengthened to six to eight months, the Commercial Times report said. They were three to six months previously.

Demand has expanded beyond GPUs to server CPUs and custom chips. Longer testing times for AI chips add pressure on packaging and test capacity. Analyst estimates cited by the newspaper expect TSMC's CoWoS monthly capacity to exceed 130,000 wafers in 2026. They expect it to reach 200,000 in 2027. Neither account said how much of any increase customers have accepted.

Equipment sales and substrate tightness

ASMPT's sales jumped 49% on AI chip packaging, startupfortune.com reported. Its core equipment unit still missed expectations.

Advanced packaging substrate availability remains tight. Lead times for some materials used in high-bandwidth memory have extended. Printed circuit board manufacturers have flagged shortages of specific laminates. High-layer-count boards need these laminates. The shortages have put upward pressure on component pricing. The ASMPT number points the same way. The money is moving toward the back end of the chip line. For buyers, the constraint sits at assembly and test as much as at the front end.

What to watch next

Analysts have pointed to utilisation rates at cloud providers as potential risks to the buildout. They also cite the long lead times needed to turn model improvements into revenue-generating applications. Several firms said customers are willing to commit to volume guarantees. They do so in exchange for secured supply.