Intel Foundry says advanced packaging is among the main constraints on AI scaling

Intel Foundry said power delivery, connectivity, advanced packaging and supply chain resilience are becoming the primary constraints on AI scaling. The company made the case in a Semiconductor Engineering article based on a presentation at the Global Semiconductor Alliance European Executive Forum.

The shift matters because the industry spent years focused on transistor scaling. Intel Foundry said the biggest challenges now extend beyond the transistor, as AI systems combine more compute, memory and interconnects in one package.

From system-on-chip to system of chips

Intel Foundry described a move from the system-on-chip model, where one chip integrated as much functionality as possible, to a system of chips. That approach uses chiplet architectures to combine multiple specialized dies, memory stacks and accelerators into a single solution. Intel Foundry said the model offers greater modularity, scalability and faster innovation cycles for advanced AI workloads.

The company also tied the change to three AI trends. Agentic AI introduces multistep reasoning workloads that are less predictable than traditional computing and place new demands on power delivery and high-performance connectivity. Physical AI brings intelligence to edge devices and real-world systems, where scalable automation and modeling are needed for cost-effective, high-yield manufacturing. Sovereign AI initiatives increase demand for secure, resilient and geographically diverse manufacturing and supply chains.

Intel Foundry said it is addressing the constraints on two fronts: developing advanced process and packaging technologies, and using AI and machine learning in technology development and manufacturing to improve quality, accelerate yield learning and help customers bring products to market faster. It also pointed to UCIe, a standardized interconnect for high-bandwidth, low-latency communication between chiplets, as a way to simplify integration of heterogeneous systems.

Supply stays tight

The packaging constraint is already visible in the supply chain. BriefAsia reported that advanced packaging substrate availability remains tight, and that printed circuit board makers have flagged shortages of specific laminates required for high-layer-count boards, putting upward pressure on component pricing. The same report said capacity reservations for advanced packaging and leading-edge logic nodes extend well into next year, and several firms said customers are willing to commit to volume guarantees in exchange for secured supply.

Suppliers are still expanding. BriefAsia reported that multiple firms across the AI supply chain have announced fresh investment in manufacturing capacity, spanning chip fabrication, advanced packaging, optical components and data centre infrastructure. In Taiwan, multiple packaging houses are expanding interposer and chip-on-wafer-on-substrate capabilities to meet demand for high-bandwidth memory integration and multi-die modules.

Prices and capacity

Prices are moving. The Commercial Times reported on Tuesday that foundries and outsourced semiconductor assembly and test providers were preparing CoWoS price increases of 10% to 20%, according to industry sources. The report said demand has expanded beyond graphics processing units to server central processing units and custom application-specific integrated circuits, while longer testing times for AI chips are adding pressure on packaging and testing capacity.

Equipment lead times have lengthened to six to eight months from three to six months previously, the Commercial Times report said, as chipmakers prioritise delivery schedules and suppliers struggle to expand production quickly. Analyst estimates cited by the newspaper expect TSMC's CoWoS monthly capacity to exceed 130,000 wafers in 2026 and reach 200,000 in 2027.

Verification is another bottleneck. Semiconductor Engineering reported that multi-die assemblies now require a combination of simulation, emulation and FPGA prototyping, rather than simulation alone, to ensure that entire systems work as expected.

For AI chip buyers, the constraint shifts the focus from transistor density to whether advanced packaging, substrates and interconnects can be supplied at volume. Intel Foundry's argument is that those system-level pieces now sit alongside process technology as limits on how fast AI systems can scale.