AI chip packaging capacity grows as CoWoS prices are reported to climb

Buyers of AI accelerators face packaging prices reported to be rising by 10% to 20%, and equipment lead times of six to eight months mean new lines cannot arrive quickly. What stays unknown is whether the reported CoWoS increase happens at all: the figures came from industry sources quoted by the Commercial Times, not from a TSMC announcement.

Capacity keeps going in

The money is still moving. BriefAsia reported on 3 November that multiple firms across the AI supply chain announced fresh manufacturing investment in recent weeks.

The commitments span chip fabrication, advanced packaging, optical components and data centre infrastructure, according to the same report. Third-quarter results showed revenue and margin improvements tied to AI orders, and several companies cited order visibility into the first half of 2027. In Taiwan, multiple packaging houses are expanding interposer and chip-on-wafer-on-substrate capabilities. South Korean memory makers have pulled forward next-generation high-bandwidth memory timelines, with clean-room space coming online ahead of earlier schedules.

That is a lot of capital chasing one bottleneck.

The price signal from CoWoS

The Commercial Times reported that foundries and outsourced assembly and test providers were preparing 10% to 20% increases for chip-on-wafer-on-substrate packaging, Investing.com wrote on 27 October. Demand has spread beyond GPUs to server CPUs and custom ASICs, while longer testing times for AI chips add pressure on packaging and test capacity. Equipment lead times have lengthened to six to eight months from three to six months previously.

No company has confirmed those numbers, and no effective date has surfaced.

How much capacity is coming

TSMC's CoWoS monthly capacity is expected to exceed 130,000 wafers in 2026 and reach 200,000 in 2027, according to analyst estimates cited by the Commercial Times.

The packages themselves are getting bigger. AI chip packaging sizes are approaching four times the reticle limit, with the 2.5D roadmap battle extending to 2028, biggo reported on 27 October. Equipment suppliers are already feeling it: ASMPT's sales jumped 49% on AI chip packaging, Startup Fortune reported on 27 October, while its core equipment unit missed.

India's smaller bet on mature packaging

Sahasra Semiconductors' facility in Bhiwadi, Rajasthan, involved an investment of more than ₹1.5 billion, about $15.8 million, according to a government announcement. The plant covers 5,295 square metres and has a stated annual packaging capacity of 60 million units, or roughly 164,000 units a day. Tata Electronics' ₹270 billion, about $3.25 billion, OSAT facility in Assam has an approved capacity of 48 million units a day. CG Power's ₹76 billion Sanand plant is planned for 15 million units a day. Kaynes Technology's ₹33.07 billion Sanand facility is designed for more than 6.33 million units a day.

Consultant Nitin Dodia estimated a facility focused on mature packaging technologies could be built for ₹1.5 billion to ₹2 billion, about $15.8 million to $21 million. He told EE Times a new OSAT should secure at least one customer committed to buying over three to five years. Without that anchor, equipment sits idle.

What stays tight

Advanced packaging substrate availability remains tight, and lead times for some materials used in high-bandwidth memory have extended, BriefAsia reported.

Printed circuit board manufacturers have flagged shortages of specific laminates needed for high-layer-count boards, which has put upward pressure on component pricing. Memory suppliers have responded by prioritising high-bandwidth memory over commodity DRAM. That shift carries implications for server and consumer electronics buyers.